Too late to protect memory IP theft; predictive maintenance; IP for AI; CFET transistor innovation, manufacturing IP tests process. Continue reading »

The Robustness Validation approach in design of automotive memory components addresses reliability and safety margins between design and actual application. By John Blyler, Editorial Director, JB Systems Improved reliability is just one of the benefits claimed in using the supply-chain sensitive … Continue reading »

Criticalblue’s CEO David Stewart reveals how software driven hardware performance optimization moved them beyond the chip design world. Continue reading »

Solid state drive (SSD) chip complexity and embedded software for Internet of Things (IoT) cloud data renews need for prototyping platforms. Continue reading »

Two distinct IP functional groups vie for strong growth in the future. Which one will win? Continue reading »

"No! I refuse to die. My memory is stored on the newest Cadence microchips, unlike some I won't name." - Private ATM Continue reading »

As IP leads semiconductor growth, subsystem blocks cause node-based cost challenges, verification issues, hidden embedded cores, interface preferences and more. Continue reading »

Counterfeit memory chips may be the cause of Russia’s Phobos-Grunt space mission failure. Perhaps a truly system-level verification approach is needed. Continue reading »

It’s funny how interface questions rarely have straight-forward answers. For example, ask ARM and OCP about interfaces for shared memory on heterogeneous multicore SoCs. Politics aside, there are reasons why the answer to that question leads to a variety of other questions. For one thing, the original question assumes an equivalence that does not exist. Read on, if you want the entangled details. Continue reading »