The Design and Verification Conference and Exhibition (DVCon U.S.) held earlier this year once again brought chip developers together with EDA tool vendors to tackle major issues. Continue reading »

The first day of the Design and Verification Conference and Exhibition (DVCon) is dedicated to the updates and short tutorials from the standards body that supports it – Accellera Systems Initiative. Continue reading »

Contestants at the Cadence-Accellera Portable Stimulus Specification (PSS) contest during DAC made changes to verification tests in record time. Continue reading »

Yatin Trivedi, DVCon Chair, talks about Internet-of-Things verification issues and differences between standard specifications and implementations efforts. By John Blyler, Editorial Director As the general chair of the upcoming semiconductor chip design and verification conference (DVCon), Yatin Trivedi discusses the … Continue reading »

Debugging the debug; UPF; digitizing sound; testing assertions; occupant aware homes; embedded verification; uninitialized variables; and glow-in-the-dark DDR4. Continue reading »

A panel of experts from Dassault Systemes, ARM, Cadence and IPextreme turned a critical eye to the management of IP in the Google-on-Air event. Continue reading »

Former EDA industry expert makes the case for pre-silicon testing using post-silicon tools. What part will IP play? Will design and test languages be a problem? Continue reading »

Automotive giant Daimler wrestles with the best way to incorporate hardware-software verification and integration tools in future designs. Continue reading »

While researching examples of pure vs. embedded software verification, I chanced upon the Pure software IP division of Imagination Technology. Continue reading »

The left-hand side of the systems-engineering Vee-diagram is where hardware and software subsystems really come together. But in what context? Continue reading »