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Complex Instruction Set Computing (CISC) processors derive their performance from a set of instructions that are capable of executing multiple low level operations.
A coprocessor supplements the functions of the primary processor, which may include floating point arithmetic, signal processing, graphics, or encryption.
A macrosequencer is a flexible processor that can be reconfigured to a different algorithm on demand and is often used in reconfigurable computing machines.
Other IP includes many additional types of Processor IP
Reduced Instruction Set Computing (RISC) processors derive their performance from a large set of simple uniform instructions that can be executed quickly.
Very Long Instruction Word (VLIW) processors take advantage of instruction set parallelism controlled by the compiler to simplify the hardware.
GF 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
Popular MIPS family of multi-threaded (MT), multi-core, 32-bit processors
WiFi Platform (802.11a/b/g/n/ac from 1x1 to 2x2)
Half-cluster Power Series7XE GPU including OpenGL ES 3.x, DX9_3 Feature Level, OpenCL
Strategic opportunity to access Leadership iPTV/STB/DTV SoC Design Data Bases
SMIC 90nm High Density Standard Cell Library - HVT, 1.2v operating voltage