Home > Log In
Log In
PLB Bus Structure
IP Preview
Name:
PLB Bus Structure
Provider:
Xilinx
Description:
PLB Bus Structure
Overview:
The 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write and read data path units with a three-cycle-only arbitration feature. It contains ...
Category:
Additional data available! Portability, process node, maturity, features, and more can be viewed by logging in with your ChipEstimate.com account.
To see the entire IP datasheet from Xilinx please log in or register.
Please log in to continue
Please log in to continueNew user?
Latest Semiconductor IP
WEA2244PD45G
weasic
WEA2630FE45G
weasic
WEA1214OS45G
weasic
WEA7681PD22G
weasic
WEA7186PD55S
weasic
Most Popular IP
VCM0990G022
Vidatronic
General purpose, low jitter fractional-N PLL
Silicon Creations
M31 PCIe 5.0 PHY IP for Storage and High Bandwidth Connection
M31 Technology Corporation
DDR-PHY-TCI-TN28HPCP-DDR43PHY
True Circuits
MEERKAT_1_SLG_IN-CHIP_MONITORING
Dolphin Design
SDRAM DDR3/2 & LPDDR3/2 Hardened PHY - TSMC 65nm
Dolphin Technology