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dwc_arcv3_hs_shared_memory_option

Synopsys

L2 cache/cluster shared memory option for multicore versions of ARC HS5x and HS6x processors

The DesignWare ARC HS66 and HS68 processors feature a dual-issue, 64-bit superscalar architecture for use in embedded applications where highperformance and high clock speed are required. ...