Log In
Description:
Silterra 0.11um ULL Single-Port/Dual-Port SRAM, Single-Port Register File and Via ROM Compiler
Overview:
VeriSilicon SMSB 0.11um Ultra-Low-Leakage(ULL) Process Synchronous Memory Compiler optimized for Silterra Malaysia Semiconductor Manufacturing Corporation (SMSB) 0.11um ...
Additional data available! Portability, process node, maturity, features, and more can be viewed by logging in with your ChipEstimate.com account.
To see the entire IP datasheet from VeriSilicon please log in or register.
Please log in to continue
Please log in to continue
New user?