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Integrating Analog IP in 28-nm Processes
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Manuel Mota — Synopsys

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The economics of the system-on-chip (SoC) development are, for the most part, objective and well understood: industry-wide trends establish the advantages of integrating more functions into the same chip and this, in turn, drives the scaling down of process technology nodes.

A virtuous cycle is established, where advanced process technologies enable higher levels of integration and the need for higher integration drives the development of even finer process technologies. This cycle is clearly reflected in Moore's Law: for each new product in a new process generation, all the functionality of the previous product is implemented and more functional blocks are added to build increasingly complex functionality. This trend is not questioned - it is an axiom.

In terms of circuit implementation, designers must port all of the existing functional building blocks into the new process generation, sometimes with additional improvements that take advantage of higher performance enabled by the process characteristics.

Register transfer logic (RTL) is agnostic to process technology node, so porting digital functionality is not perceived as problematic. However, analog functionality is perceived as more challenging because of its closer dependency on the process characteristics. The decision to integrate analog and digital functions has different dynamics: at each new node, the debate over whether to integrate analog into the SoC is rekindled until, predictably, the economics of the industry validate integrating analog in the new node and the debate is decided in favor of integration. Successful mixed-signal SoCs in all previous process technology nodes have demonstrated this cycle.

The three major arguments concerning analog block integration in advanced process technologies are relevant and deserve being analyzed in detail, in order to understand why they are incorrect:

Argument 1: The economics of analog integration don't add up

Digital circuitry benefits process technologies' scaling. New process technologies mean finer geometries, smaller areas, faster circuits and, typically, lower dynamic power dissipation. However, analog circuitry does not scale in the same way. The performance requirements for analog blocks, especially in terms of linearity, mean the function is easier to implement using well understood thick oxide devices at I/O supply level. As this type of device has not changed for many generations of the process (for example, 2.5 V-oxide devices were introduced in the 250 nanometer (nm) process and are still available in some 28-nm processes), the total area of the analog block that uses them is also more or less constant.

In this case, the argument is that the relative portion of the very expensive real estate allocated for the same function in new process technologies keeps increasing, and therefore the cost also increases to a point where the integration of that analog function is no longer justified.

This argument sounds correct in theory. But in fact, advances in analog circuit techniques over the last 10 years have resulted in new and innovative techniques that challenge this argument. For example, digitally assisted analog architectures, digitally calibrated architectures, and other dithering and randomization techniques can, through digital processing, eliminate most of the non-idealities inherent to deep submicron devices. This simplifies the circuit, making it more robust and gaining performance while using only thin-oxide devices.

By reducing analog complexity and taking full advantage of process characteristics, these techniques enable scaling the area and power of the analog block, by process technology node, to a level close to what is expected on digital blocks. Therefore, the economics of integration is positive to analog block integration. Most systems end up integrating them to improve their competitive position in the market.

Argument 2: The risk of analog integration is too large

Given the huge development costs for new products in advanced process technology nodes, risk mitigation is a very important factor in the decision processes. Analog blocks are often judged too immature and risky for integration in new process technologies.

Advanced process technology nodes pose new challenges to the development of the integrated circuits. In particular, some performance characteristics of analog blocks rely on specific characteristics of the process. For example, device matching and output impedance suffer larger variations due to layout dependent effects such as well proximity effect (WPE) and shallow trench isolation (STI) stress. These and other ageing effects are prevalent on advanced process technology nodes and have the potential to degrade the circuit performance. All of these effects must be taken into account during the architecture and design phases.

Digitally assisted analog architectures alleviate the performance requirements and thus make these blocks less sensitive to those process effects. In addition, thorough design validation flows ensure that the all effects are accounted for during the design phase.

System architects minimize the risk of system implementation, by using pre-validated IP blocks from trusted IP partners. The partners they choose must understand the design requirements and have the capability to implement heavy, tool-intensive design validation flows and provide silicon-validated IP in advanced nodes.

As the cost of the fabrication increases, system architects find the argument to include pre-validated analog and mixed-signal IP even more compelling. The tradeoff associated with using an existing IP block that has adequate characteristics is largely compensated by the risk mitigation derived by it being silicon validated.

Argument 3: Development cycles are incompatible with time-to-market window

In advanced process technology nodes, design validation flows become lengthy and tool intensive. Thousands of simulation runs are necessary to cover all corner and functional cases, including statistical variations. This extensive, but necessary, validation process could impact the time to market of a product. This highlights the importance of re-using off-the-shelf analog IP.

The re-usable analog IP blocks should be, at the same time, generic (to cover a wide application space) and specific (to limit any cost penalty to the system due to potential over-specification). These apparently incompatible constraints can be addressed by implementing analog IP blocks that are configurable.

The concept of configurable IP is well known in the digital space. It relies on the deployment of a complete set of sub-blocks that are validated together, but that optionally can be implemented or left out of the final configuration, depending on the specific system requirements.

In the analog space as well, designers can use specific, validated sub-blocks that implement alternative functions together to configure a final product that matches the specific requirements of the system. As analog IP typically is used as physical hard macro, the sub-blocks seamlessly abut without requiring further intervention or risk. This is illustrated in Figure 1, where two specific configurations of the analog-to-digital converter (ADC) core –one including optional complex functionality and the other including an input buffer--are obtained by combining optional blocks that are pre-validated together.

Figure One

Synopsys has applied the concept of configurable analog IP to several classes of products ranging from high-performance DesignWare® Data Converters to complete Analog Front-Ends and Audio Codec sub-systems. In these products, characteristics such as the number of channels and the type of analog interface and drivers can be configured. This IP enables SoC creators to create validated analog IP products that match their specific requirements, thus ensuring that they can integrate analog IP into their advanced process technology products, and improving their position in the market.

Since SoC designers validate the configurable analog sub-blocks together and no new design is needed, the development time for any specific configuration is minimal. They validate the final design, ensuring that it offers effective area use and power dissipation for each system's needs.

Applying product configuration concepts to the analog block development, coupled with a system definition that allows for the use of off-the-shelf analog IP, makes the decision to integrate analog IP easier due to the short time-to-market as well as the significant reduction of risk.


The case for analog integration has been debated and won on every process technology node transition, and the move to 28nm and beyond is the same. Successful SoC designers understand the economic and development risks involved and the technological advances that mitigate them. The availability of trusted, validated analog IP that can be configured to application needs simplifies these decision processes and allows for a much faster time-to-market.

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Synopsys delivers semiconductor design software, intellectual property (IP), design for manufacturing (DFM) solutions and professional services that companies use to design systems-on-chips (SoCs) and electronic systems. The company's products enable semiconductor, computer, communications, consumer electronics and other companies that develop electronic products to improve performance, increase productivity and achieve predictable success from systems to silicon


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About the Author

Manuel Mota

Manuel Mota, Technical Marketing Manager for Data Converter IP within the Solutions Group at Synopsys, has worked in the semiconductor industry for more than 10 years as analog IP designer for Chipidea Microelectronica (Portugal) with responsibility for the design of PLL and Data Conversion IP cores as well as complete Analog Front-Ends for communications. He later assumed the role of Business Developer for Data Conversion products with the responsibility of product definition and pre-sales technical engagement with customers. He joined Synopsys from MIPS Technologies in May 2009, assuming the Technical Marketing Manager role. Manuel holds a PhD in Electronic Engineering from the Lisbon Technical University which he completed while working at CERN (Switzerland) as a Research Fellow. He has authored several technical papers and presented in technical conferences on analog and mixed signal design.