Recent announcements of FinFET roadmaps accelerated the discussion about the opportunities and challenges associated with the use of FinFETs in IP design. It also opened up the discussion about the future of CMOS scaling all the way down to 7 nanometers (nm).
FinFET technology alleviated several important challenges associated with continued scaling of planar bulk CMOS, but other challenges related to lithography such as tolerances associated with double-patterning mask alignment, as well as reliability and performance concerns associated with aging, continued to get more acute with every scaling step.
In this article we will discuss the design opportunities and challenges stemming from the introduction of the FinFET device and link them to the manufacturing and reliability challenges and complexities associated with further scaling.
FinFET: An IP Designer's Device of Choice
Due to its many superior attributes, especially in the areas of performance, leakage power, intra-die variability, low-voltage operation (translates to lower dynamic power), and significantly lower retention voltage for SRAMs, FinFETs are replacing planar CMOS as the device of choice.
In a planar FET a single gate controls the conductive channel. Such a gate does not have good electrostatic field control away from the surface of the channel next to the gate, resulting in leakage currents between source and drain even when the gate is off. By contrast, in a FinFET the transistor channel is a thin vertical fin with the gate fully "wrapped" around the channel formed between the source and the drain. The gate of the FinFET can be thought of as a "multiple" gate surrounding the thin channel. Such a multiple gate can fully deplete the channel of carriers. This results in much better electrostatic control of the channel and thus better electrical characteristics.
Figure 1: Planar FET vs. FinFET
The most relevant geometric parameters of a FinFET are its height H, its width (body thickness) Tsi, and its channel length L. The electrical width of a FinFET is twice the height plus the width.
At any one technology node FinFETs have several advantages over its planar counterpart, including mainly:
FinFETs as an Opportunity for IP Design
Design metrics of performance, power, area, cost, and time-to-market have not changed since the inception of the IC industry.
Designing in FinFET broadens the design window. Operating voltage continues to scale down, significantly reducing dynamic and static power. Additionally, short channel effects are significantly reduced, decreasing the guard-banding needed to deal with variability, and performance continues to improve (compared to planar at an identical node).
For memory designers, an added advantage of FinFETs is the significantly lower retention voltage of FinFET-based SRAM compared to that of planar.
FinFET Design: The Challenges
The FinFET is a significantly more complex device to model. Accurate FinFET parasitic extraction is more complicated. Generating good, yet compact, SPICE models is also more challenging than for planar devices. For most design activities the aforementioned complexities are transparent to the designer.
FinFETs have a lower DIBL/SS (sub-threshold swing) that is a desirable characteristic as far as leakage is concerned. On the other hand, the undoped (or very lightly doped) and practically fully-depleted channel renders the use of body biasing techniques commonly used in planar less effective, making alternatives necessary.
The finite granularity of the fin width W and the limited range of freedom in channel length for a given architecture make optimizing analog as well as digital design more complex. Granted that many fins can be "ganged" together to generate a desired W, still L and W are not exactly free continuous parameters. Also, FinFETs have a significant number of restricted design rules (RDR).
For SRAM design, optimizing the β ratio of a bit-cell is more difficult as "W" is quantized, and the flexibility in "L" as a tuning parameter is limited. Practically speaking, a β of "1" or "2" are the two main choices available. That, in turn, creates the need for more advanced assist techniques to enhance SRAM yield.
FinFET: Lithography and Manufacturing
Given the fact that EUV will not be ready for volume production any time soon, the use of double-patterning (DP) is a must for all layers with tight pitches. This is not unique to FinFET. In fact, it applies mostly to interconnect layers (BEOL), which are the same in planar and FinFET technologies.
At nodes below 22 nm, the concept of digitizing a whole active area and then using a "cut-mask" to generate the desired geometry is a direct result of mask alignment challenges associated with double-patterning. For circuits like SRAMs and sense amplifiers mismatches are intolerable.
For a 6T-SRAM, with horizontal misalignment one pair of devices results in a reduced L (fast but very leaky), while the other pair results in a wider L (weak devices). Similarly, for vertical misalignment the mismatch is in W of the devices. Bottom line: you run the risk of having non-functional silicon.
To alleviate this problem the scheme of digitizing the contiguous gate layer and then using a cut mask to ensure proper printability is used. Clearly this approach results in the most satisfactory printout for devices. Also, it's noteworthy that this approach of using a "cut mask" is not a FinFET-specific technique and applies to the formation of devices for planar as well as FinFET beyond 20 nm.
FinFET design has a disproportionate number of RDRs. Lithography is only one reason for these RDRs: the fin patterning/formation process with the high aspect ratio etches and the fragility of the fins under the high stress necessary for mobility enhancements are further factors driving high restrictions.
A FinFET manufacturability rule (to alleviate severe performance consequences) worth mentioning specifically is the rule associated with "lonely" FinFETs. Given the 3D nature of the fins, the SiGE stress profile of a P-device loses all effectiveness when the device is not part of a cluster. Therefore, it's necessary to enforce strict dummy device clustering rules to ensure proper performance of active P-type FinFETs.
Figure 2: TCAD simulated stress profile of a lonely P FinFET
Aging is related to the physics of the high-K dielectric gate stack and is by no means a FinFET phenomenon, yet FinFET designers have to deal with this reliability concern in the form of simulating and accounting for the effects of negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) aging that alters the behavior of the device. The industry's experience (history) in this area is unfortunately limited and it's an added variable to deal with.
NBTI, which impacts P-type devices and PBTI, which impacts N-type devices, are a shift (deterioration) in the threshold of the device, Vt, that is a function of Vgs, temperature, and time. It's a partially reversible process that depends on the time a device is on and the corresponding duration of recovery (device off). It's highly sensitive to high temperature. Over years of use a device threshold could shift significantly impacting the delay of a critical path by as much as 7 to 10 percent. NBTI is much more critical than PBTI and NBTI is an order of magnitude higher than PBTI.
FinFET: Soft Error Rate
Soft Error Rate (SER) upsets caused by impinging particles are an important parameter to monitor, especially for SRAMs. How does SER look as we move from planar to FinFETs? The answer is simply: better.
Simply explained, charge generation caused by energetic impinging particles is in the substrate. In planar, a lot of it can reach the drain of the device and collect there, causing enough current to upset the storage node. In FinFETs, the conduction is mainly in the channel and, thus, most of the charge dissipates in the substrate and will not collect at the drain, making the probability of upset much lower.
Summary and Conclusions
FinFET device technology is the most promising technology for extending Moore's law all the way to 7 nm. It offers excellent solutions to the problems of sub-threshold leakage, poor short-channel electrostatic behavior, and high device parameters variability that plague planar CMOS. Furthermore, its ability to operate at lower supply voltage has extended voltage scaling, which had been leveling off, and allows further static and dynamic power savings.
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