SoC test has become very complex. The combination of increasing design sizes, the growing use of IP and greater design complexity has made SoC testing a challenge. As designs become larger, the traditional full chip test methodologies are proving increasingly challenging due to power consumption and long test development times that make testing of large SoCs inefficient. Designers need a test solution that can effectively test their large designs, which contain a variety of IP and design blocks, while maintaining low test cost and high productivity.
Another key trend that has a direct impact on SoC test complexity is the growing use of IP. Not only does IP account for larger portions of the design, but there is an enormous variety of IP being used, like DDR, PCIe, HDMI, USB and memory IP, and each of these different IP can be used multiple times in the SoC. Soft IP configured as digital logic block or digital logic cores further add to SoC test complexity. While this heterogeneity is excellent for designs that need to incorporate a variety of functions, it requires some consideration from the test perspective: how will the IP and digital logic blocks be integrated for test and accessed from the top level of the SoC? And how can the entire design be tested without increasing test time and cost?
Fig 1: The amount of IP used in a design is significantly growing with each technology node, requiring an efficient solution to integrate and test at the SoC level
Finally, the increasing size and complexity of designs is driving design teams to implement a hierarchical design approach in which teams that are often globally dispersed each work on their piece or block of the design, making it necessary to have standard and unified interfaces and sign-off at each design hierarchy for easy integration at the SoC level.
What’s Missing in Most Test Integration Solutions
Most current ad hoc IP test integration solutions are based on in-house scripting and rely on direct access to I/Os. This was a viable solution in the past when a typical design had a few IP whose I/Os could be brought out directly at the SoC level. However, with larger designs, more IP and a limited number of I/Os, direct testing of the entire design is not feasible.
Designers must choose a test solution that is capable of handling large hierarchical designs efficiently. The current top-down DFT approaches using centralized test management or control are not as effective when considering hierarchical designs, because they add area while increasing design time and test costs. This makes it all the more necessary to employ a hierarchical DFT approach for test, similar to the hierarchical implementation of the other design steps. In this scenario, as different design blocks or hierarchies are completed in various parts of the world by different teams, each design team can easily handle their design block by signing off on test in the same way as they would sign off on timing or any physical aspect of the design, and then assemble those blocks into a single unified design. As design size increases, both the test pattern development time and the amount of time required to test the entire SoC increase significantly. It is not uncommon for designs to be over 100 million gates, requiring weeks for developing test pattern at SoC level. In addition to hierarchical DFT implementation, it is also necessary to have the ability to reuse the test patterns at the IP or block level and then automatically port those patterns to the SoC level and test the entire SoC, without having a need to generate patterns at the SoC level.
A New Paradigm
An effective hierarchical test solution provides an area-efficient and unified framework to access all the IP and digital logic blocks, and also has the ability to port the IP or block-level patterns to the SoC level, eliminating the need to regenerate the patterns. By supporting multiple broadly adopted IEEE standards such as IEEE 1500 and 1149.1, the solution provides an efficient infrastructure and gives user the flexibility to utilize it in test and debug environments throughout the design lifecycle. By leveraging IP or block-level diagnostics and providing SoC-level diagnostics it can pinpoint exactly which test failed and where the failure occurred, which helps reduce the overall design and production ramp-up time. Tester-based flows are, of course, cost intensive; an interactive solution that runs on a work station and interfaces directly to the chip enables users to quickly bring up their designs in a lab setup or at their desk without requiring expensive tester time.
Key Requirements of a Comprehensive Hierarchical Test Solution
There are a few key steps to consider with hierarchical testing, including accessing each of the IP or digital logic blocks, SoC test integration of all the blocks, pattern porting, test scheduling and diagnostics.
Fig 2: Key Steps in an Effective Hierarchical SoC Test Solution
It starts by providing a standard interface to integrate and access each of the IP and digital logic blocks in the SoC. The IEEE 1500 standard is the de-facto standard for IP- or core-based test and provides a flexible means of interacting with each of the individual IP and digital logic blocks. A solution that leverages any existing IEEE 1500 interfaces, and also has the ability to create them with optional wrapper boundary registers (WBR) for IP and blocks that don't already have them, enables a standard communication channel with all the IP and blocks from the SoC level.
Fig 3: IEEE 1500 standard interface
Once all the IP are wrapped with IEEE 1500 interfaces, they have to be integrated as part of SoC. The ideal solution will create an efficient hierarchical IEEE 1500 network to integrate the individually wrapped IP or digital logic blocks, and will provide hierarchical control using modular test access control blocks. By using a ring or daisy-chain architecture combined with modular test access control, the design hierarchies can have a single IEEE 1500 interface instead of having an interface for every IP at each design hierarchy level, minimizing the top-level routing and congestion.
After the SoC has been assembled, the test infrastructure has been created and all the IP have been integrated, it is time to create test patterns at the SoC level. A solution that allows reuse of the IP and block-level patterns eliminates the need to create new patterns at the SoC level. With such a solution, the test patterns that are supplied with the IP would be ported to the sub-chip or design block hierarchy with the help of the IEEE 1500 network and modular test access control. Similarly, when the sub-chip is integrated within the SoC environment, those sub-chip level patterns are ported to the top level, allowing test engineers to reuse the IP-level patterns, as well as verify the patterns and do a test signoff at each of the design hierarchies at which they are working. The automatic porting of the patterns to the SoC level where they can be directly applied to the tester saves significant development time and resources. In addition, the increased controllability and observability at the periphery of the IP and logic blocks with the IEEE 1500 wrapper significantly improves test QoR and diagnostics.
Fig 4: The STAR Hierarchical System is an automated hierarchical test solution to efficiently test SoCs. It significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level.
Test cost is a key concern with today’s large and increasingly complex designs. Flexible test scheduling is fundamental to minimizing test cost. Scheduling, if not properly managed, can result not only in increased test time and cost, but can also have an impact on other design parameters such as power consumption during test. A solution that provides the flexibility to program any possible schedule to test different IP and digital logic blocks serially or in parallel, allows the designer to configure a test schedule that is optimal both in terms of test time and power consumption. A solution using reduced pin count at the top-level e.g. JTAG TAP, can help further reduce test time by enabling multi-site or concurrent testing, where multiple dies are tested in parallel.
Finally, the ability to diagnose the silicon failures quickly can help ramp-up production much faster. A good hierarchical SoC test solution should be able to provide detailed tester-based and interactive diagnostics solutions for silicon bring-up and characterization.
To meet the demand for methods of efficiently testing large designs, Synopsys offers a comprehensive portfolio of design and silicon test solutions that provide higher quality, reliability and yield. It includes the STAR Hierarchical System, which leverages the test structures inside all the individual building blocks of the design, including logic, memory, interface IP, or analog mixed-signal (AMS) blocks, to provide hierarchical access and the ability to test each building block from the SoC level. Synopsys' hierarchical test solution provides all the capabilities needed to increase productivity, lower test cost and improve overall test quality of results, including IP test integration, the ability to re-use IP test patterns, user programmable flexible test scheduling, and advanced tester-based and interactive silicon failure diagnostics. By utilizing the industry-standard IEEE 1500 and 1149.1 interfaces and the proposed P1687 standard, the STAR Hierarchical System creates area and routing efficient infrastructure to hierarchically test and debug today's complex SoCs and effectively addresses the challenges of traditional test methodologies.
Synopsys delivers semiconductor design software, intellectual property (IP), design for manufacturing (DFM) solutions and professional services that companies use to design systems-on-chips (SoCs) and electronic systems. The company's products enable semiconductor, computer, communications, consumer electronics and other companies that develop electronic products to improve performance, increase productivity and achieve predictable success from systems to silicon