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Building on the success of the award-winning Aptiv generation of CPU cores, Imagination is now busy designing the next generation of MIPS processors. Codenamed Warrior, the MIPS Series5 CPUs feature cores based on the MIPS32 and MIPS64 instruction set architectures, with a focus on superior performance efficiency across the high-end, mid-range and entry-level/microcontroller CPUs.
Warrior P-class MIPS P5600 CPU delivers leading 32-bit performance
The P-class MIPS P5600 is the first member of the highly anticipated MIPS Series5 Warrior CPU family from Imagination. The P5600 CPU IP core is a best in class processor that addresses all four aspects that matter in mobile: efficiency, performance, area and features.
Leading performance delivered efficiently
The MIPS P5600 CPU has been designed to be a leader in high performance and power efficiency for 32-bit processor IP. It offers 1.2 - 2x more system performance than its proAptiv predecessor in a similar mobile-focused power envelope, and supports peak frequencies above 2GHz on TSMC's 28HPM process node.
MIPS P5600 CPU IP core
Here's a breakdown of what to expect from the MIPS P5600 CPU:
- Industry-leading single thread performance for high-end 32-bit CPUs (exceeding 5 CoreMark/MHz and 3.5 DMIPS/MHz, per core) at significantly lower power than its competitors
- Up to 30% area savings at the cluster level and 40% savings at the core level relative to similar performance competition, enabling it to achieve higher performance at reduced area
- A comprehensive feature set that includes virtualization, 128-bit SIMD, 40-bit eXtended Physical Addressing (XPA), scalable security, and more
The MIPS P5600 IP core is a balanced design that uses techniques such as load/store bonding, reading registers after issue (so no reservation station logic is required), and right-sized schedulers to efficiently achieve maximum utilization of the 16-stage pipeline and its superscalar, multi-issue out-of-order microarchitecture.
MIPS P5600: Efficient performance from a balanced design
In addition to this high-performance pipeline and new features of 128-bit SIMD, virtualization, and XPA, the MIPS P5600 CPU has additional attributes designed to execute large, highly complex workloads, including:
- Large (> 1000 entry) TLB resources
- Best in class, advanced branch prediction mechanisms
- Enhanced Virtual Addressing (EVA) for more flexible usage of virtual address space, providing easy and efficient use of memory for larger footprint Linux implementations
MIPS P5600 highlights: EVA and XPA, the MIPS SIMD Architecture (MSA) and full hardware virtualization
MIPS P5600 implements EVA and XPA, two technologies that have been created to stretch the limits of traditional 32-bit architecture addressing in response to the increasing code size footprints of mobile and connected consumer devices. But they go well beyond the needs of those segments.
XPA is a new feature which extends the amount of addressable physical memory in devices to a maximum of 1 Terabyte, offering larger address space for applications that might need it. While the P5600 CPU was designed first and foremost for the needs of application processing in smartphones, tablets, DTVs and connected consumer devices, the performance/power profile and extensive feature set extend the reach of this CPU core into additional markets , including a variety of networking applications such as residential gateways, 802.11ac routers, CPE modems, microservers, and various functional network appliances.
MIPS P5600 is the first Warrior CPU to implement three new features of significant relevance for modern processors: SIMD, hardware page table walking, and hardware virtualization.
The MIPS SIMD Architecture (MSA) features 150+ instructions, and was designed for use and code development in high-level languages such as C++ or OpenCL. As an example, the MIPS SIMD instruction set directly covers 100% of all compiler vector operations in the gcc compiler toolchain, which also leads to maximum auto-vectorization benefits on existing code. In addition, it provides a unique, faster exception model which means less work is required for exception processing.
On the virtualization side, MIPS P5600 implements full hardware virtualization, with support for many more than two independent operating systems running as guests, with no modification, fully isolated from each other. It includes features that address virtualization needs at the system level, including virtualized I/O and interrupt processes per execution environment.
Virtualization has traditional use in servers needing many nodes operating separately in parallel, but the use of this technology is expanding into an increasing variety of applications. It can also be used for mixed mode Linux and real-time environments in separate domains, with open source application processing in one, with real-time, latency sensitive tasks running in another, with QoS/priority.
MIPS P5600 supports full hardware virtualization
Current security solutions in phones and other connected consumer devices are limited. Unlike the limited choice provided by competitors between one secure and one insecure world, with MIPS there is a choice of numerous secure worlds. The isolation of each virtualized execution environment from the next is one key for security solutions going forward. Technology supporting multiple security contexts lays a foundation for building comprehensive and scalable security solutions that address the needs for next generation mobile and connected devices, enabling them to access secure content from multiple providers, make secure payments, and ensure identity protection across multiple applications and content sources.
New MIPS M5100 and M5150 Warrior M-class processors for 32-bit MCUs
The newly-announced MIPS M51xx (M5100 and M5150) processors are two important members of the Series5 Warrior family, the most exciting generation of CPUs in the recent history of MIPS. Both M5100 and M5150 are fully synthesizable CPU IP cores that focus on delivering leading performance efficiency and a unique feature set for the MCU and embedded markets.
The feature set of the MIPS M5100 and M5150 processors
When it was first introduced in 2012, microAptiv offered an incredibly powerful and flexible solution that delivered the ultimate best in class CPU performance and incorporated the low power principles of the MIPS32 architecture and microMIPS ISA.
Based on the valuable feedback gathered from deploying the market-leading microAptiv range to our customers, our engineering team has worked tirelessly to improve on what made microAptiv so amazing while incorporating the latest features in the MIPS Release 5 Architecture.
The new MIPS M5100 and M5150 CPUs share the same 5-pipeline design that sits at the core of microAptiv, while adding a few elements to the mix:
M5100 and M5150 are the only MCU-class CPU IP cores that feature hardware virtualization. This unique feature provides increased security and reliability for a wide range of applications. With virtualization, multiple, unmodified, operating systems and applications can run independently and securely at the same time on a single, trusted platform. Designers can take advantage of this to develop systems that provide a secure path to deliver updates/downloads, and benefit from enhanced IP protection.
MIPS M51xx CPUs support multiple guest operating systems
A very useful example of how companies can use this feature is related to wearables. Once integrated into a wearable device, M5100 or M5150 could be used to implement a multiple-guest environment where one guest running a real-time kernel manages the secure transmission of sensor data, while another, under RTOS, can provide the audio and graphics capabilities.
- FPU (optional)
The FPU complies with single and double precision IEEE 754 standards and supports IEEE-754 2008 Nan and ABS instructions. The unit includes a dedicated 7-stage pipeline that operates in parallel with the core integer pipeline. Most instructions execute with 1 cycle throughput and 4 cycle latency, making it ideal for real-time applications that make extensive use of maths coprocessors.
- Ultra-secure debugging (optional)
The new M-class cores include anti-tamper features that provide an additional layer of security against potential external attacks. A secure debug feature prevents external debug probes from accessing the core internals so an application's code stays safe and secure inside the core at all times.
Thanks to these characteristics, the MIPS M5100 and M5150 low-power processors greatly expand Imagination's technology lead for MCUs, both in performance and feature set.
Flexible designs for the next wave of embedded computing
MIPS M5100 is designed to handle all MCU application-specific requirements and provides real-time performance. It is optimized for lower-cost, highly low-power MCUs where every square millimeter of area matters.
A block diagram of the MIPS M5100 CPU
MIPS M5150 incorporates a high performance L1 cache controller and virtual memory management support. The memory management unit enables it to power high-performance embedded systems that can execute operating systems with virtual memory support such as Linux.
A block diagram of the MIPS M5150 CPU
Finally, the two processors include the same powerful DSP engine that was present inside microAptiv, while our innovative microMIPS ISA is there to provide up to 30% code compression for applications where memory size is critical.
Conclusion
The features presented above, together with a series of micro-architectural improvements and design innovations, give the MIPS Series5 Warrior CPU family the upper hand in the battle for supremacy in the microprocessor space. P5600 and M51xx are the first cores in a wave of Series5 Warrior CPUs that will bring our pure RISC architecture across a range of 32-bit and 64-bit variants with a focus on superior performance efficiency for apps processors, real time CPUs, MCUs and other embedded offerings.
Moving forward, we are committed to growing the available CPU IP portfolio and provide our partners with the latest features in the dynamic world of CPU IP. The upcoming MIPS Series5 Warrior generation of cores will grow to feature 64-bit variants and implement a series of compelling architectural features so stay tuned for the next wave of releases and partner announcements!
