I. INTRODUCTION
In the majority of CMOS image sensors, high performance analog-to-digital converters are employed to produce digital outputs. Most CMOS image sensors have ADC resolutions of 10 to 12 bits. In addition, sampling rates of tens to hundreds of MS/s are required for high resolution (5Mega pixels and higher) and to enable real-time high definition video capture. The power consumption of these high performance ADCs is a major issue, as it can significantly reduce the battery life, and also raise the die temperature, which degrades image quality due to the higher leakage and noise.
There are several different architectures for the signal path in image sensors, including the use of a single ADC, the 2- and 3-ADC architectures, and employing an array of ADCs. The single ADC architecture is shown in Fig. 1(a). In this architecture, a single ADC digitizes all pixels. The advantage of this architecture is the smaller die area and the absence of image artifacts due to mismatches between multiple ADCs. In addition, this architecture provides the lowest die yield loss due to ADC nonlinearity caused by component mismatches. Random mismatches in transistors and capacitors impact the linearity of ADCs. Tighter matching tolerance thus larger die area would be required per ADC in multi ADC architectures if a comparable die yield to a single ADC architecture were desired. The disadvantage of the single ADC architecture is the high sampling rate requirement in the ADC, especially for high resolution image sensors, which generally translates into high power consumption per conversion.
Fig. 1. Three architecture types for the signal path in an image sensor. (a) Single-ADC architecture, (b) 2-ADC architecture, and (c) Multi-ADC architecture.
Several image sensors include multiple ADCs to reduce the sampling rate requirement. For Bayer-pattern color image sensors, there are twice as many green pixels as red or blue pixels. For these sensors, it is possible to use 2-ADCs in parallel where one ADC exclusively processes the green pixel, and the other ADC is multiplexed between the red and blue channels (Fig. 1(b)). The advantage of this 2-ADC architecture is that the sampling rate requirement of each ADC is half that of the single ADC architecture. The lower sampling rate generally improves the power efficiency and reduces the overall power consumption. Since all of the same color pixels are processed by the same ADC, there are no image artifacts due to ADC mismatches. The disadvantages of the 2-ADC architecture are the increase in overall ADC die area and the yield loss. It must be noted that this architecture is most appropriate for Bayer-pattern color image sensors. In a 3-ADC architecture, a dedicated ADC is employed for each color group, which further improve the power consumption at the cost of increased die area and yield loss.
Some image sensors employ an array of ADCs to further reduce the power consumption of ADCs as shown in Fig. 1(c) [1]. Typically, one ADC is multiplexed between a number of columns, between 2 to16 columns. The primary advantage of such a multi-ADC architecture is low overall power consumption. However, in the majority of implementations, there are significant disadvantages to this approach including image artifacts due to ADC mismatches and much larger area. In addition, the die yield loss can be substantial.
Cambridge Analog Technologies (CAT) has developed innovative technologies to overcome the challenges of power consumption, die area, and yield. The fidelity advantages of a single, 2-, or 3- ADC architectures is exploited while achieving the low power consumption and throughput of a multi-ADC architecture. CAT’s proprietary technologies further improve the die yield and the reduce the die area beyond conventional implementations.
II. PUMA: Ultra-Low Power A/D Conversion Technology
PUMA (Precision Ultra Micro-power Amplification) technology [2] is the driving force behind CAT’s ultra-low power ADCs. PUMA is used to implement ultra low-power switched capacitor circuits, which are used in pipelined ADCs suitable for image sensors. Most switched-capacitor circuits process the analog signal through a sequence of simple mathematical functions and modest interstage gains. For precision applications such as high resolution ADCs, it is critical for the error in these interstage gains to be very small. Typically, power-hungry high-gain high-speed operational amplifiers (op-amps) placed in feedback are utilized to achieve these precise gains by driving the input voltage to ‘virtual ground’. Op-amps, however, are becoming increasing difficult to design and excessively power hungry in modern deep submicron processes. PUMA technology is based on the principle that the accurate output voltage and associated accurate virtual ground condition is necessary only at the sampling instant. As shown in Fig. 2, the op-amp is replaced by a zero crossing detector which senses the moment the virtual ground condition is achieved, and causes the sample of the output voltage be taken at that moment. The ‘driving’ of virtual ground is now replaced by ‘sensing’ of virtual ground, which is far more power efficient, allowing an order of magnitude reduction in power consumption.
Fig. 2. Schematic explaining PUMA circuit technology, where a power hungry op-amp in feedback is replaced with a simpler and much lower power “virtual-ground”/zero-crossing detector.
CAT’s PUMA technology enables high performance ADCs and is suitable for all three types of image sensor architectures shown in Fig. 1. CAT’s ADCs offer an order of magnitude lower power consumption and smaller area compared with conventional ADCs. For this reason, a single-ADC architecture can be realized at low power even in high resolution image sensors. For example, a 14 Megapixel imager operating at 15 frames/s [3], (high resolution digital motor drive, for example) can utilize a 12 bit, 210 MS/s ADC [4]. As the ADC consumes minimal power even at full speed, the die temperature rise will not be an issue. Such an ADC could also be used for full 1080p, 60fps video capture when operating at 120 MS/s. In addition, the PUMA technology can be applied to the switched-capacitor programmable gain amplifier (PGA) for the similar savings in power and area. Further power savings can be achieved with a 2-ADC architecture for a minimal additional area.
Another technique, commutative feedback capacitor switching (CFCS) (U.S. Patent #5416485, licensed exclusively to CAT) allows for improved differential linearity while reducing area and power consumption. In imaging applications, differential nonlinearity (DNL) in ADCs can create undesirable image artifacts. Typically, achieving DNL at a 12 bit level requires large capacitors or calibration. Large capacitors invariably increase power consumption and area while calibration also adds complexity in the system and usage as well as increases power consumption and area. The CFCS technique allows excellent DNL even with small, thermal noise limited capacitors without increasing power consumption or circuit complexity. The input capacitance is also much lower than conventional ADCs, reducing the power consumption of the S/H amplifier or PGA that must drive the ADC input capacitance.
CONCLUSION
With the combination of PUMA and CFCS, CAT’s ADCs occupy a tiny footprint and consume minimal power consumption. CAT’s high performance ADCs can be used in a single-ADC architecture and consume almost no power, or be used in an ultra-high performance multi-ADC architecture without the severe area, power and noise problems typically encountered in conventional multi-ADC architectures.
REFERENCES
[1] J. W. Yang, et. al, “A 3 Megapixel Low-Noise Flexible Architecture CMOS Image Sensor”, Digest of Technical Papers, International Solid-State Circuits Conference, Feb. 2006.
[2] Eliminating the Analog Bottleneck – Cambridge Analog Technologies’ Ultra Low Power High Performance Analog/Digital Conversion, CAT Whitepaper 2010
[3] Omnivision OV14810 Product Brief
[4] Please contact CAT at ip@cambridgeanalog.com for availability and ordering.
