In modern digital electronics, analog circuits are an integral part of System on Chip (SoC) solutions for many applications such as wireless and wireline communications, consumer, automotive and medical devices. Many of these applications demand low power dissipation. Technology scaling has benefited performance and power dissipation of digital circuits; however, for analog circuits, technology scaling has not led to as great benefits. In fact, scaling has resulted in analog circuit performance becoming the bottleneck in many applications. Cambridge Analog Technologies has successfully broken this analog bottleneck to achieve an order of magnitude lower power dissipation for analog-to-digital converters (ADCs) and other switched capacitor circuits.
Traditionally, many analog circuits in mixed-signal environments have relied upon operational amplifier (op-amp) based signal processing. Op-amps have long been regarded as a ‘silver bullet’ for analog circuits, as op-amps reduce sensitivity to circuit non-idealities, but this robustness comes at the cost of significant power consumption. In 2005, researchers at MIT, led by Prof. Hae-Seung Lee, co-founder and chairman of Cambridge Analog Technologies, developed new comparator based switched capacitor (CBSC) and zero-crossing based circuit design methodologies for sampled-data systems that eliminate the use of op-amps while equaling or exceeding the robustness associated with op-amp based circuits [5,6].
In addition to robustness, there are several key advantages of zero-crossing based circuits over op-amp based circuits. Since comparators or zero-crossing detectors are open-loop circuits, there are no stability concerns. Therefore, an arbitrary number of low gain stages can be cascaded to realize high gain. Moreover, high gain can be obtained by positive feedback or dynamic techniques that cannot be used in op-amps due to the stability concerns and its continuous-time nature. This makes zero-crossing detectors much more amenable to deep submicron technologies than op-amps. In addition, as explained in later sections, zero-crossing based circuits are fundamentally much more power efficient than op-amp based circuits. The simplicity of comparators relative to op-amps, in particular minimal biasing and no need for frequency compensation, and lower inherent noise, suggest potentially more than an order of magnitude lower power consumption over conventional op-amp-based techniques at the same performance levels.
Precision Ultra-Micro Power Technology
High precision switched-capacitor circuits, as found in numerous modern electronics in devices such as analog-to-digital converters, filters and other analog signal-processing circuits, rely on accurate charge transfer between capacitors. The process of transferring charge accurately between capacitors has been conventionally accomplished through the use of high gain, high speed operational amplifiers (op-amps) placed in feedback, wherein the op-amp drives its inverting terminal to a virtual ground condition in a continuous time fashion (Fig 1). Comparator or zero crossing based switched-capacitor circuits (CBSC)[5,6] is based on the observation that in a discrete-time switched-capacitor circuit, an accurate output voltage of a given switched-capacitor stage is necessary only at the end of a clock cycle or at the sampling instant of the following switched-capacitor stage. Since the “inverting input” needs to be at virtual ground only at the sampling instant of the next stage, driving that node to virtual ground in a continuous time manner using an op-amp is neither necessary nor power efficient.
Fig. 1. Traditional Pipeline Analog to Digital Converter (ADC) Stage utilizes an op-amp in feedback to force its input to a virtual ground condition. This process forces charge transfer from capacitor C1 to C2. However for high precision ADCs, the op-amp needs both very high gain and high speed at the same time. This dual requirement is very difficult to achieve in modern sub-micron processes. CAT’s PUMA™ technology eliminates the op-amp leading to order of magnitude reduction in power dissipation.
Fig. 2. Cambridge Analog Technologies PUMA™ Technology utilizes a Zero Crossing Detector instead of an op-amp to dramatically reduce power consumption for the same precision. The voltage at output of the stage is ramped across the voltage range of the circuit. The Zero-Crossing Detector then detects the exact instant when its input crosses zero and sends a signal to the next stage to stop sampling the output of this stage. Since this technique doesn’t rely on stacked devices or on large transistor intrinsic gain, it is much more compatible with modern deep-submicron devices. It is also simpler and robust across process variation.
In PUMA™ technology, the op-amp is replaced by a comparator or a zero-crossing detector as shown in Fig. 2. The comparator detects the instant the “inverting input” crosses virtual ground as the output of that stage is ramped from low to high. The comparator output is then used to determine the instant when the next stage samples. Since the comparator only detects the virtual ground condition rather than having an op-amp force that condition, it is much more power efficient. A general purpose comparator can be built much more power efficiently than an op-amp; however, this virtual ground detector can be built even more efficiently since unlike a general purpose comparator, it needs to only detect a zero-crossing; additionally, the input voltage signal of this comparator is a monontonic predetermined constant slope ramp. Zero-crossing based switched-capacitor circuits are much more power efficient than conventional switched-capacitor circuits, typically consuming an order of magnitude less power at the same speed, precision and signal to noise ratio.
CAT has developed a multitude of numerous additional circuit techniques to make zero-crossing based circuits faster, more accurate, and robust so that they can be deployed to cover a large application space. Advanced two-phase techniques, overshoot control, ramp linearization, ramp rate control, fast and high PSRR zero-crossing detection, and novel reference charging schemes have been deployed making these designs highly robust against process and temperature variations and against noise from digital circuits. In addition, these techniques enable ADC performance to 14+bits and 200+MS/s at extremely low power consumption.
In order to study the full potential of Comparator and Zero-Crossing Based circuits, comparative analysis has been performed. The results of the analyses can be obtained in the Proceedings of IEEE, included in its entirety in Appendix A of reference #. The summary of the theoretical comparison is shown in Table I, where typical power consumption normalized to the theoretical minimum power consumption Plim is shown for conventional switched-capacitor circuits, CBSC, and ZCD-based circuits. As shown in Table I, comparator based and zero-crossing based circuits have potentially up to two orders of magnitude lower power consumption compared with conventional approaches.
Table 1: This table illustrates the ratio of power consumption of circuits built using op-amps versus those built using zero-crossing and comparator based techniques. Theoretically it is possible for two-orders of magnitude savings in energy use by utilizing zero-crossing based ADCs.
Comparator Based Circuits and Zero-crossing Based circuits have been demonstrated and publically disclosed by CAT and MIT researchers in numerous premier conferences and journals [1-6]. The first publication of a single ended Comparator Based ADC was first published at the 2006 International Solid-State Circuits Conference (ISSCC), where it won the Jack Kilby Outstanding Student Paper award . The performance and power efficiency have been steadily improving since then.
The first differential zero-crossing detector (ZCD) based pipeline ADC was presented at the 2008 Symposium on VLSI circuits. The fruit of collaboration between CAT and Samsung Electronics, the prototype achieved 10b, 26 MS/s performance at 153 fJ/step FOM . At the 2009 International Solid-State Circuits Conference (ISSCC), a more advanced differential ZCD based pipeline ADC was reported by MIT researchers . The prototype chip achieved 12b 50MHz performance at 88 fJ/step FOM. The most recent results, to be presented at 2010 Symposium on VLSI Circuits, achieve 12b/100MS/s at 53 fJ/step FOM with 10.2-ENOB at Nyquist input frequency . These FOMs are far better than any reported results in a similar performance category. Cambridge Analog Technologies has developed more advanced differential zero-crossing based circuits for high resolution, low power applications. The proprietary patented technologies allow robust operation despite device variability and noisy system-on-a-chip (SOC) environments. Recent designs completed at CAT implementing these proprietary technologies indicate 12 bit (>10.5 ENOB), 100MSPS performance in a production environment is feasible at less than 5mW of power consumption (excluding digital I/O’s). The corresponding FOM is better than 35fJ/step.
Application and Impact
CAT’s PUMA™ technology can be leveraged for a large reduction in power and/or enhanced functionality in numerous applications. High precision analog circuits including analog-to-digital data converters are essential building blocks in modern electronics. They are required in applications such as wireless communications, wire-line communications, sensor based control and monitoring such as temperature, pressure, vibration, MEMS, and touch screen, audio applications, video applications, and portable medical imaging. According to an estimate from Gartner Dataquest (2008), two billion ADC chips will be shipped per year at 19% combined annual growth rate (CAGR) by 2013.
Lower power consumption is an essential specification in the majority of these portable applications. Ever increasing appetite for higher wireless communication data speeds, richer functionality and portable digital gadgets requires higher speed and higher resolution data converters. Applications such as wireless communications (WiFi, WiMax, LTE), digital video, personal area networking, automotive and set top boxes are real growth engines for the semiconductor industry.
The power reduction of PUMA™ can be utilized in building analog-to-digital converters with higher precision/resolution eliminating the need for complex filtering prior to data conversion. Filters, typically, consume a large amount of area typically and simplifying them can yield large area and cost reduction.
CAT’s technology can also enable power efficient 10G Ethernet for which 12b, 1GS/s ADC’s are desired. Due to the confined space, heat dissipation is of great concern. At present, no single ADC can reach the required performance for the desired power consumption. CAT’s technology can lower the power consumption by 10-15X down to a few hundred milli-watts.
Due to the potentially extreme low power consumption in these circuits, new electronic system architectures such as software defined radio and cognitive radios that have been impractical presently may become feasible. The key bottleneck in realizing a software defined radio is a low power, high performance A/D converter. A radio that can digitize large chunks of the spectrum and thus enable multiple standards in a single radio requires an ADC with a sampling rate of multiple GHz and resolution of 12 bits or more. A conventional ADC would burn several watts to achieve this; CAT’s low power technology can enable dramatically reduced power consumption.
CAT’s PUMA™ technology leverages a revolutionary zero-crossing and comparator based technique that allows for an order of magnitude reduction in power consumption for analog-to-digital converters at the same precision. These robust converters are much more compatible with deep-submicron CMOS processes than traditional op-amp based circuits because they do not rely on stacked devices or on large intrinsic transistor gain. By providing additional functionality or an order of magnitude reduction in power, CAT’s ADCs will enable a wide range of new applications in modern SoCs.
This work is based in part on support provided by National Science Foundation Grant No. 0839225. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the National Science Foundation.
 J. Chu, L. Brooks, and H.-S. Lee, “A Zero-Crossing Based 12b 100MS/s Pipelined ADC with Decision Boundary Gap Estimation Calibration,” to be presented at VLSI Symposium, Hawaii, June 2010
 H.-S. Lee and C. G. Sodini, “Mixed-Signal Integrated Circuits-Digitizing the Analog World,” Proceedings of IEEE, vol. 96, pp. 323-334, Feb. 2008.
 L. Brooks and H.-S. Lee, “A 12b 50MS/s Fully Differential Zero-Crossing-Based ADC Without CMFB,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2009, pp. 166-167.
 S.-K. Shin Y.-S. You, S.-H. Lee, K.-H. Moon, J.-W. Kim, L. Brooks, and H.-S. Lee., “A Fully-Differential Zero-Crossing-Based 1.2V 10b 26MS/s Pipelined ADC in 65nm CMOS, ” Dig. of Tech. Papers, Symposium on VLSI Circuits, pp. 218-219, June 17-20, 2008.
 L. Brooks and H.-S. Lee, “A Zero-crossing based 8b 200MS/s pipelined ADC,” in ISSCC Dig. Tech. Papers, San Francisco, CA, Feb. 2007, pp. 460-461
 T. Sepke, J. K. Fiorenza, C. G. Sodini, P. Holloway, and H.-S. Lee, “Comparator-Based Switched-Capacitor Circuits For Scaled CMOS Technologies,” IEEE J. Solid-State Circuits, vol. SC-41, pp. 2658-2668, December 2006.