Tom Hackett — Cadence
"Custom standard" is surely an oxymoron, yet that term exactly describes the standard interfaces that frame virtually every system on chip (SoC) currently in development. Once-stable interface standards are now evolving at an accelerating rate. This rapid rate of change is having a huge impact on intellectual property (IP) selection. A new requirement set is supplanting the old standbys - performance, power, and area (PPA). To understand this, we need to take a fresh look at the unexpected force that propelled the current level of commercial IP adoption, and brace for the powerful impact that will hit virtually every SoC design in the coming year.
The past dozen years have seen the rise of several interface standards that now dominate electronic product development. PCI Express, USB, Ethernet, ARM's Advanced Microcontroller Bus Architecture (AMBA), and the Double Date Rate (DDR) memory interface have become universally deployed standards during this period. As expected, the conformity of design imposed by these standards drove a huge end-product economy of scale, resulting in a vast array of interoperable hardware and software components.
Figure 1. Evolution of the DDR memory interface standard
The economy of scale brought on by the rise of standard interfaces made it initially quite cost-effective to develop IP in-house and re-use that IP across multiple products. As we look about today, however, we see that IP is most often acquired from commercial IP developers. What drove this change? While it has been argued that commercial IP developers deliver an economy of scale by amortizing development costs over a larger number of SoC projects than captive IP developers, that argument alone is not a sufficient cause. It does not hold true without the added force of changing requirements. In fact, captive development is always the most cost-effective solution if the IP changes little from generation to generation. Think of this as the develop-once, use-many principal. This is intuitively less costly than paying for the same IP on project after project.
The migration to commercial IP was driven primarily by the ongoing evolution of the interface standards that the IP embodied. When faced with design-once, use-once followed by redesign-once, use-once, etc., the cost of devoting valuable engineering resources to maintain non-differentiated design components became prohibitive. It is the force of evolution, of change itself, that has driven the rise of commercial IP.
A quick look at Figure 1 helps to illustrate the underlying dynamic. This figure shows the evolution of the DDR standard from a single specification in the year 2000 to 15 different variations today, most of which can still be found in SoC designs that are currently in process. All these variations, the "custom standards", are required to serve the broad spectrum of electronic systems that now range from smartphones to servers.
In fact, it was just the gradual branching-out of the DDR standard over the first several years that drove us to today's level of commercial IP usage. The surprising, apparently accelerating branching that started to occur just one year ago will dramatically boost the need for strong commercial IP offerings to implement several new standards including DDR4, LPDDR4, Wide I/O 2, Hybrid Memory Cube (HMC), and High Bandwidth Memory (HBM).
This recent and rapid proliferation of standards is impacting the other mainstay interfaces as well. Figure 2 shows the recent new variants of PCI Express, USB, AMBA, and display interfaces that must be comprehended by new SoC design projects.
Figure 2. Recent evolution of popular interface standards
The result of this explosion of standard interface variations, each uniquely customized to end-product requirements, will not only drive an increased usage of commercial IP, but it will demand a wide variety of IP implementations, each optimized for the intended application. SoCs will not be able to deliver on end-product requirements without flexible, optimal, high-quality IP that surpass today’s offerings.
To achieve economy of scale and maintain the benefit of increasing maturity from each project served, yet still optimize for an increasing variety of applications, IP must be architected to be easily customizable. Each application needs to be individually optimized for performance, power, and area. Furthermore, the IP development process must be highly automated to enable rapid incorporation of feature changes, whether they are driven by the evolving standards or changing project requirements.
The tailoring of standards to meet a variety of applications is also driving IP to be application focused. This means that IP must be assembled into optimized subsystems targeted for specific applications. For example, a LPDDR3 interface for a smartphone may need to be integrated with a Mobile PCI Express interface or combine a MIPI CSI (camera) or DSI (display) interface as well. An application-focused subsystem enables optimal performance for a given application.
Since optimized subsystems are required, and these must be integrated with other subsystems and perhaps with customer-supplied IP, ease-of-integration is a key concern. This entails integration into popular design tool flows and support for a variety of semiconductor processes.
The technology business has always been about consistently delivering superior features and periodically introducing the next big thing. Being first to market is a huge advantage and IP is now on the critical path to incorporating the latest standards. Early availability of IP supporting new standards and consistent improvements of that IP to maintain a technology edge are now more important than ever.
Verification IP Requirements
Verification IP (VIP) is an important companion to any design IP offering. VIP is used to perform pre-silicon verification of IP subsystems and SoCs. VIP components are arrayed into a virtual testbench around an SoC and used to drive digital simulations. This functional verification approach validates compliance with interface standards and can verify the data flow across an SoC, as well as compliance with interconnect fabric specifications.
If early availability is important for IP, it is even more important for VIP. The new IP controllers and PHYs need to be verified, and independently created VIP is the best method for doing so. Leading commercial VIP components have hundreds of built-in protocol checks that automatically scan for protocol violations during simulation runs. These checks, along with libraries of test scenarios, enable pre-silicon verification many months before a product goes to a plug fest.
In order to be used to verify a design, the VIP itself must be known-good - that is to say, mature. But how can this be achieved when working with new protocols? First, the new VIP may be a successor product that reuses known-good components from a previous generation. This reduces the potential for error but does not eliminate it, since there is likely to be a significant amount of new code as well. The only way to deal with this is early development and testing. A leading VIP provider will begin development at an early stage of a new specification before SoC designs are underway. Then, by working in partnership with the first wave of SoC developers, the VIP may grow into maturity along with the earliest SoC prototypes. Mainstream adopters then benefit by having fully mature VIP to assist them with SoC verification.
Integration in the VIP context means integration into the test environment that will be used to verify the SoC. Since there is a diversity of simulators and specialized verification languages in use today, the VIP needs to support all the popular options.
Finally, VIP is increasingly expected to deliver productivity aids in addition to basic modeling capability. Test suites, debugging aids, simulation acceleration options, and performance analysis features are now part of advanced VIP deliverables.
The recent and rapid diversification of interface standards is enabling end-products that are optimized for their target applications. However, this diversification is also driving new requirements for IP and VIP. A new generation of IP and VIP products is needed to meet these requirements and thus enable SoC developers to gain a market advantage.
To see how Cadence is addressing this challenge with next-generation IP and VIP, please visit http://www.cadence.com/ip/Pages/default.aspx
Also, join the conversation about new memory standards such as DDR4, LPDDR4, Wide I/O 2, HMC, and HBM. Register for a live online chat session with Cadence memory experts on September 17. Send an email to firstname.lastname@example.org to reserve your spot.